HY5DU283222AQ Datasheet, PDF (26/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AQ
Burst Read terminated by another Burst Read
Read command terminates the previous Read command and the data is available after CAS latency for the new com-
mand. Minimum delay from a Read command to next Read command is determined by /CAS to /CAS delay (tCCD).
Timing diagram is shown in Fig.6.
Fig.6. Burst Read terminated by another Burst Read
/CLK
CLK
CMD
tCCD
READ (A) READ (B)
DQS
DQ
Burst length =4, CAS latency =2
A0 A1 B0 B1 B2 B3
Read(A) is term inated and Read(B) data out starts
Burst Write terminated by another Burst Write
Write command terminates the previous Write command and the data is available after CAS latency for the new com-
mand. Fastest Write command to next Write command is determined by /CAS to /CAS delay (tCCD). Timing diagram is
shown in Fig.7.
Fig.7. Burst Write terminated by another Burst Write
/CLK
CLK
CMD
tCCD
WRITE (A) WRITE (B)
DQS
DQ
A0 A1 B0 B1 B2 B3
Burst length =4, CAS latency =2
W rite(A) is terminated and W rite(B) data in starts
Rev. 0.2 / Sep. 2003
26