HY5DU283222AQ Datasheet, PDF (41/51 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

Timing Diagram
HY5DU283222AQ
Data Input (Write) Timing (BL=4)
DQS
DQ
DM
tDQSL
tDQSH
tDH
tDS
DI n
tDH
tDS
DI n = Data in for column n
3 subsequent elements of data in are applied in the programmed order following DI n
Don’t care
Data Output (Read) Timing (BL=4)
/CK
CK
DQS
DQ
tDQSCK max
tQH
DQ n
tDQSQ and tQH are only shown once, and are shown referenced to different edges of DQS, only for clarify of illustration.
tDQSQ and tQH both apply to each of the four relevant edges of DQS.
tQHmin = tHPmin - X where ;
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL)
X consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern
effects, and p-channel to n-channel variation of the output drivers.
Rev. 0.2 / Sep. 2003
41