HDMP-2689 Datasheet, PDF (9/28 Pages) Agilent(Hewlett-Packard) – Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes

9.4 ns
Tx_H
TCn
TDn[9:0]
Tx_CDH
Case A. Tx Half Rate SDR Timing
9.4 ns
Tx_H
Tx_H
TCn
TDn[9:0]
Tx_CDH
Tx_CDH
Case B. Tx Full Rate DDR Timing
Test Conditions: V_IH = V_DDQ, V_IL = GND
Figure 9. Transmitter Timing Diagram.
Table 4. HDMP-2689 Transmitter Section Timing Characteristics,
T_C = 0°C to T_C = 85°C, V_DDQ = 2.3 to 2.7 V, V_DD = 1.7 to 1.9 V, V_DDA = 1.7 to 1.9 V
Symbol
Parameters
Units Min Typ Max
1G
Tx_CDS[1,2]
Clock to data skew time; the data must be stable by T_CDS after the clock edge to
ps
300
guarantee correct clocking of the data
Tx_H[2]
Hold time; the time after the clock edge until which the data must remain stable
ps
2000
to guarantee correct clocking of the data
t_TXlat_buffer^[3] Transmitter latency; the time between the latching edge of the transmit byte clock
ns
80
TCn and the leading edge of the first transmitted serial output bit in buffer mode
bits
85
t_TXlat_codec^[3] Transmitter latency; the time between the leading edge of the transmit byte clock
ns
90
TCn and the leading edge of the first transmitted serial output bit in codec mode
bits
95.5
2G
Tx_CDS ^[1,2]
Clock to data skew time; the data must be stable by T_CDS after the clock edge to
ps
300
guarantee correct clocking of the data
Tx_H[2]
Hold time; the time after the clock edge until which the data must remain stable to ps
2000
guarantee correct clocking of the data
t_TXlat_buffer^[3] Transmitter latency; the time between the latching edge of the transmit byte clock
ns
65
TCn and the leading edge of the first transmitted serial output bit in buffer mode
bits
138
t_TXlat_codec^[3] Transmitter latency; the time between the leading edge of the transmit byte clock
ns
70
TCn and the leading edge of the first transmitted serial output bit in codec mode
bits
149
Notes:
1. This clock-to-data skew time is equivalent to –300ps setup time.
2. Measurement conditions were V_IH = V_DDQ, V_IL = GND.
3. Due to the FIFO which aligns the phase of the internal chip clock with the transmit byte clock (TCn) and the asynchronous nature of the chip reset, the
typical latency varies; a maximum of the typical range is given.
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