HDMP-2689 Datasheet, PDF (23/28 Pages) Agilent(Hewlett-Packard) – Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes

Pin List, continued
I/O DEFINITION
Name Pin
Type
Signal
RDD0 K15
RDD1 L16
RDD2 M17
RDD3 J14
RDD4 K16
RDD5 K17
RDD6 J16
RDD7 H15
RDD8 H16
RDD9 H17
RXAP A01
RXAN B01
RXBP A03
RXBN B03
RXCP A15
RXCN B15
RXDP A17
RXDN B17
TXAP A05
TXAN B05
TXBP A07
TXBN B07
TXCP A11
TXCN B11
TXDP A13
TXDN B13
TCA
M03
TCB
T07
TCC
P10
TCD
M15
TDI
F04
TDO
F03
TMS
F02
TCLK F01
TRSTN G04
TDA0 P03
TDA1 R02
TDA2 M04
TDA3 P02
TDA4 L04
TDA5 T01
TDA6 N02
TDA7 K04
TDA8 M02
TDA9 P01
TDB0 P09
TDB1 U08
TDB2 T08
TDB3 R08
TDB4 P08
TDB5 U06
TDB6 T06
TDB7 T05
TDB8 P07
TDB9 R06
O-SSTL2 Receive Data Pins, Channel D: Parallel data on this bus is valid on the rising and falling edges of RCD. See Table 2 for
interpretation of this bus under different PMX settings. (See Figure 8 for termination)
HS_IN Received Serial Data Inputs: 0.01 µF AC-coupled high-speed differential inputs (see Figyre 5).
HS_ OUT Transmitted Serial Data Outputs: 0.01 µF AC-coupled high-speed differential inputs (see Figyre 5). Note, if high speed
output driver is disabled, then both outputs are held at Logic 1.
I-SSTL2 Transmit Byte Clock: These pins are used to latch transmit data for channels A, B, C, D into the IC. Must have the same
frequency as reference clock.
I-CMOS
O-CMOS
I-CMOS
I-CMOS
I-CMOS
Scan Test Interface: TDI is the test data input, TDO is the test data output, TMS is the test mode select, TCLK is the test
clock, and TRSTN is the test reset pin (active low).
I-SSTL2 Data Inputs: Parallel data on this bus is clocked in by TCA. See timing diagram in Figure 9. See Table 2 for interpretation
of this bus under different PMX settings.
I-SSTL2 Data Inputs: Parallel data on this bus is clocked in by TCB. See timing diagram in Figure 9. See Table 2 for interpretation
of this bus under different PMX settings.
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