HDMP-2689 Datasheet, PDF (6/28 Pages) Agilent(Hewlett-Packard) – Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes

VDDQ
FROM
CORE
OF CHIP
DIGITAL
OUTPUT
PAD
I/O
50 Ω
nominal
output
impedance
ESD
GND PROTECTION
DIGITAL
INPUT
PAD
VDDQ
TO CORE
OF CHIP
ESD
PROTECTION
GND
turnaround bits, data bits, and
an idle. The order of bit transmis-
sion is left to right as shown in
Table 8. MDIO timing is detailed
in Table 9.
The three most significant bits of
the PHY address are made up of
the hard-wired address of the
HDMP-2689. The two least signifi-
cant bits represent the channel
referenced in the frame. Two bits
are sufficient to encode IDs for
the four channels on the chip.
Figure 7. Simplified Schematic of SSTL_2 Input and Output Drivers.
HDMP-2689
VREF
Controller
0.1 µF
VREFI
VTERM (VDDQ/2)
Data Out
50 Ω
Z₀ = 50 Ω
Data In
a) Terminated SSTL_2 Connection, Rx
Figure 8. SSTL_2 I/O Terminations.
HDMP-2689
Controller
Data In
VTERM (VDDQ/2)
50 Ω
Z₀ = 50 Ω
Data Out
b) Terminated SSTL_2 Connection, Tx
Data Output and Clocking Modes
Table 5 describes the receive
parallel interface clocking. In
both half (1.0625 GBd serial )
and full (2.125 GBd serial) rate
operation, the data is always
presented as DDR, double data
rate (See Figure 11, Cases A and
B). In addition, the output clock
is always source centered (SC),
so the clock changes in the
middle of the data period. Note
that bit a, the first serial bit in a
10-bit word, corresponds to
RDn9 (see Table 2).
Configuration and Reset
The HDMP-2689 is configured by
a set of registers that can be
accessed through the standard
MII management interface
defined in IEEE 802.3 clause 22.
This interface is used by a
management entity to control
and gather status from the chip.
It is a two-wire interface made
up of a management data input/
output signal (MDIO) and a
management data clock (MDC).
Figure 15 shows the relationship
between MDIO and MDC. Figure
16 and Figure 17 present a more
detailed description of MDIO
timing. Table 8 presents the
format of a management frame
(for more information, refer to
IEEE 802.3). A management
frame consists of a minimum
32-bit preamble, a start of frame
indication, an operation code, a
PHY address, a register address,
The standard management
interface allows for 32 16-bit
registers. The HDMP-2689 sup-
ports a subset of these registers.
Management Interface Registers,
pages 26—28, show the standard
register definitions and specify
which ones are supported in the
HDMP-2689. Because the
HDMP-2689 has four physical
channels that operate indepen-
dently, some of the registers are
replicated four times, one for each
channel. Other registers are
common to all four channels, i.e.
their bit values apply to all the
channels. Still other registers are
shared between the four channels,
i.e. individual bits within a
register apply to individual
channels. The replicated registers
are accessed using a PHY address
made up of the three-bit chip ID
and the appropriate two-bit
channel ID (00, 01, 10, or 11).
Common and shared registers are
accessed using the chip ID and
the 00 channel ID. Attempting to
access common registers other
than through channel A (00) must
be avoided as it results in unde-
fined behavior. The specific
configuration and status informa-
tion that can be set or read from
HDMP-2689 is presented in the
section titled Management
Interface Registers. This section
defines the complete assignment
of management registers and
specifies which registers are
common to the four channels.
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