HDMP-2689 Datasheet, PDF (1/28 Pages) Agilent(Hewlett-Packard) – Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes

Agilent HDMP-2689
Quad 2.125/1.0625 GBd Fibre Channel
General Purpose SerDes
Data Sheet
Description
The HDMP-2689 SerDes chip
transmits and receives high
speed serial data over fiber optic
or coaxial cable interfaces that
conform to ANSI X3T11 Fibre
Channel specification. It sup-
ports SerDes-only mode using a
10-bit data interface with op-
tional 8B/10B encoding for fast
backplane applications. The
HDMP-2689 runs at 2.125 GBd or
1.0625 GBd data rates and
provides parallel-to-serial and
serial-to-parallel conversion on
four independent channels
contained in one package. An on-
chip phase locked loop (PLL)
synthesizes the high speed
transmit clock from a low speed
(106.25 MHz) reference. Each
receiver’s on-chip PLL synchro-
nizes directly to the incoming
data stream, providing clock and
data recovery. Both the transmit-
ter and receiver support differen-
tial I/O for fiber optic component
interfaces, which minimizes
crosstalk and maximizes signal
integrity. Chip control and status
are accessed via the Media
Independent Interface (MII)
defined in IEEE 802.3.
Features
• 1.0625GBd and 2.125 GBd serial
data rates
• TX and RX data rates independently
selectable for each channel
• Fibre Channel (T11) compatible
• High speed differential serial I/O
with matched 50Ω impedance
• Supports Fibre Channel Protocols
FC0
• Dual mode SerDes operation with
10-bit parallel data interface and
optional 8B/10B encode/decode
• Standard comma recognition for
positive (0011111xxx) and negative
(1100000xxx) disparity
• Source-centered, double data rate
clocking of receive parallel data
for 1.0625 GBd and 2.125 GBd
serial rates
• Source synchronous double data
rate clocking of transmit parallel
data for 2.125 GBd serial rate
• Source synchronous single data
rate clocking of transmit parallel
data for 1.0625 GBd serial rate
• MII management interface for chip
control and status
• 1.8V core power supply, 2.5V power
supply for SSTL_2 I/O
• Independent channel power-down
for power savings
• SSTL_2 compliant parallel I/O and
byte clocks
• Low transmit jitter
• Pre-emphasis on serial outputs
controllable via the management
interface
• Loss of signal detection
• AC-coupled differential LVPECL
reference clock input
• Input equalization
• Boundary scan IEEE 1149.1 compliant
• SerDes self-test capability using
PRBS or user-defined patterns
• Local internal loop back of TX
serial data to RX serial data by
channel
• 289-pin PBGA
• Testjet compliant