HDMP-2689 Datasheet, PDF (27/28 Pages) Agilent(Hewlett-Packard) – Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes

Management Interface Registers, continued
Reg 20
Rx Loss of Signal
Default
15
RX Loss of Signal (reset to 0)
N/A
14:0
Reserved
N/A
Register 20 is the RX loss of signal. It is equivalent to the LOSn pins, for channels A through D, respectively.
Reg 22
15:11
10:6
5
4:0
PVT Status Register (common)
Reserved
NEN[4:0]
Reserved
PEN[4:0]
Default
5’b00000
5’b10000
0
5’b10000
Mode
RO
RO
Mode
RO
RO
RO
RO
Register 22 is used to check the drive strengths for the SSTL_2 drivers.
Reg 23
15:13
12
11
10:6
5
4:0
PVT Control Register (common)
Reserved
Enable Fixed PVT
Reserved
NEN[4:0]
Reserved
PEN[4:0]
Default
3’b000
0
0
5’b00000
0
5’b00000
Mode
Reserved RW
RW
Reserved RW
RW
Reserved RW
RW
Register 23 is used to set the drive strength for the SSTL_2 drivers. The pull-up and pull-down drive strengths are set separately through PEN and NEN.
For proper operation of terminated SSTL_2 drivers, set PEN to 5’b11000 and NEN to 5’b01000 and set bit 12 to 1’b1. In other words, set register 23 to
16’b0001001000011000 (0x1218). If the reserved bits are not set to zero, unpredictable behavior will occur.
Reg 24
Serdes Configuration Reg 1
Default
Mode
15:2
Reserved
14’h0000
RW
1
RX Byte Align Enable
1
RW
0
SerDes Channel Enable
1
RW
Register 24 includes writeable configuration of a channel’s deserializer. Bits 15 through 2 are reserved. Bit 1, when set to logic one, causes the channel to
byte align to commas, that is, the deserializer will determine the beginning of a 10 bit byte based upon when it recognizes a comma in the serial data
stream. When bit 1 is set to zero, it will randomly determine the beginning of a byte in the serial data stream and will not realign when commas subse-
quently arrive in the serial data stream. Bit 0 is used to power down both the channel’s serializer and deserializer when set to logic 0. When bit 0 is set to
logic 0, bit 7 in register 26 must also be set to logic 0 to turn off the associated output driver, minimizing power and ensuring the high speed output is not
left in an undefined state.
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