HDMP-2689 Datasheet, PDF (11/28 Pages) Agilent(Hewlett-Packard) – Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes

HDMP-2689 Receiver Section Timing Characteristics,
T_C = 0°C to T_C = 85°C, V_DDQ = 2.3 to 2.7 V, V_DD = 1.7 to 1.9 V, V_DDA = 1.7 to 1.9 V
Symbol
Parameters
PWreset
f lockRX
B_sync_lock
B_sync_rate
1G
RX_S[1]
RX
[1]
H
t_RXlat_buffer
t_RXlat_codec
2G
RX _S ^[1]
Width of reset pulse
The time that the RX PLL takes to frequency lock to the data after reset
Bit Sync time after f lockRX
Bit Sync time after rate switch
Setup time: the time before the clock edge that the data will be stable
Hold time; the time after the clock edge until which the data will remain stable
Receiver latency; the timing between the leading edge of the first received serial
bit of a parallel data word and the leading edge of the corresponding parallel output
word in buffer mode
Receiver latency; the timing between the leading edge of the first received serial
bit of a parallel data word and the leading edge of the corresponding parallel output
word in codec mode
Setup time: the time before the clock edge that the data will be stable
Units
ns
µs
bits
µs
ps
ps
ns
bits
ns
bits
ps
RX
[1]
H
Hold time; the time after the clock edge until which the data will remain stable
ps
t_RXlat_buffer Receiver latency; the timing between the leading edge of the first received serial
ns
bit of a parallel data word and the leading edge of the corresponding parallel output bits
word in buffer mode
t_RXlat_codec Receiver latency; the timing between the leading edge of the first received serial
ns
bit of a parallel data word and the leading edge of the corresponding parallel output bits
word in codec mode
Notes:
1. Tested under load conditions described in Figure 12, with V_IH = V_REF + 0.18 and V_IL = V_REF – 0.18.
Min Typ
100
2700
1500
50
53
60
64
1200
1400
30
64
35
75
Max
500
2500
100
VTERM (VDDQ/2)
50 Ω
SSTL_2
OUTPUT DRIVER
Z₀ = 50 Ω
DELAY = 1.0 - 2.0ns
C_LOAD = 4 pF
Note: Register 23 set to 0x1218.
Figure 12. SSTL_2 Output Test Conditions.
power supplies and RFCN/
RFCP have stabilized
program MDIO
RSTN
20 µs
500 µs
f_lockRX
100 ns
PW reset
Figure 13. Externally Applied Reset (not to scale).
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