HDMP-2689 Datasheet, PDF (22/28 Pages) Agilent(Hewlett-Packard) – Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes

Pin List
I/O DEFINITION
Name Pin
Type
Signal
RSTN
DVAD0
DVAD1
DVAD2
PMX
N/C
MDIO
MDC
RFCP
RFCN
RCA
RCB
RCC
RCD
LOSA
LOSB
LOSC
LOSD
RDA0
RDA1
RDA2
RDA3
RDA4
RDA5
RDA6
RDA7
RDA8
RDA9
RDB0
RDB1
RDB2
RDB3
RDB4
RDB5
RDB6
RDB7
RDB8
RDB9
RDC0
RDC1
RDC2
RDC3
RDC4
RDC5
RDC6
RDC7
RDC8
RDC9
F05
I-CMOS Chip Reset (FIFO Clear): Active Low
F17
I-CMOS Device Address Input: 3 Bit input address with DVAD2 as MSB. Full address is the Device Address followed by the 2 bit
F16
Channel Address.
F15
D17
I-CMOS Enable CODEC or buffer mode (see Table 1)
C08, C10, N/C
E15, E16
No Connect: must be left floating.
G14
I/O-CMOS MDIO Input/Output: Used to read/write the MDIO registers.
G15
I-CMOS MDIO Clock: Input clock to the MDIO control block.
A09
I-LVPECL Differential Reference Input Clock: RFCP (+) and RFCN (-) is the106.25 MHz differential clock pins supplied to the IC.
B09
The clock ismultiplied up to generate the serial bit clock and other internal clocks. This is a LVPECL input and assumes
AC coupling and 100Ω differentialinput termination into the pad (see Figure 3).
J04
O-SSTL2 Receiver Byte Clocks: Each receiver drives a 106.25 MHz or 53.125 MHz receive byte clock RCn.
T03
N12
H14
G02
O-SSTL2 RX_LOS, Channels A–D: Receive channel loss of signal.
M05
If RXnP/N ≥ 300mV peak-to-peak differential, LOSn = logic 0
M13
If 150 mV < RXnP/N < 300mV, LOSn undefined
G16
If RXnP/N ≤ 150 mV peak-to-peak differential, LOSn = logic 1
K03
O-SSTL2 Receive Data Pins, Channel A: Parallel data on this bus is valid on the rising and falling edge of RCA. See Table 2 for
L02
interpretation of this bus under different PMX settings. (See Figure 8 for termination)
M01
K02
K01
J02
H04
H03
H02
H01
U04
O-SSTL2 Receive Data Pins, Channel B: Parallel data on this bus is valid on the rising and falling edge of RCB. See Table 2 for
P06
interpretation of this bus under different PMX settings. (See Figure 8 for termination)
T04
R04
N06
P05
U02
P04
T02
N04
R12
O-SSTL2 Receive Data Pins, Channel C: Parallel data on this bus is valid on the rising and falling edge of RCC. See Table 2 for
U16
interpretation of this bus under different PMX settings. (See Figure 8 for termination)
P12
T14
T15
R14
P13
P14
T16
N14
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