HDMP-2689 Datasheet, PDF (26/28 Pages) Agilent(Hewlett-Packard) – Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes

Management Interface Registers
Notes: All registers from 0 to 31 not mentioned below are reserved and should not be accessed.
RO means read only (any value written will be discarded).
RW means the value can be read or written.
Reserved RW means the value should always be written with the indicated default value.
The 2689 responds to four consecutive device addresses, corresponding to the four channels of the device. For example, if the DVAD[0:2] input pins are
set to 101, then channel A responds to 10100, channel B responds to 10101, channel C responds to 10110, and channel D responds to 10111. Any
information which is not specific to one channel (this includes the information in registers 2, 3, and 19) is obtained and/or set via channel A (in this
example, device address 10100). These registers all contain “(common)” in their description. Accessing the common registers through any channel other
than channel A results in undefined behavior and must be avoided.
Reg 2
15:0
PHY_ID part A (common)
Organization ID
Default
16’h0033
Mode
RO
Reg 3
PHY_ID part B (common)
Default
15:10
Organization ID
6’h0B
9:4
Manufacturer’s Model No.
6’h03
3:0
Rev. No.
4’h1
Registers 2 and 3 are static values that identify the part, and should be read from channel A. They are read-only values.
Mode
RO
RO
RO
Reg 17
Speed and Configuration
Default
Mode
15
Transmit Full/Half Speed Control (1=Full)
1
RW
14
Receive Full/Half Speed Control (1=Full)
1
RW
13
Enable Comma Edge Alignment (1: Aligned to particular edge, 0: No specific alignment)
Inverse of PMX pad value RW
12
Comma Edge Alignment (1: positive edge, 0: negative edge)
0
RW
11
Enable Internal Loopback (same function as register 25, bit 13)
0
RW
10
Include CDR Lock in RX_LOS
0
RW
9:0
Reserved
10’h0
Reserved RW
The transmit full/half speed control is used to set the transmit path of a channel to either a 2.125 GBd serial rate (when set to logic one) or a 1.0625 GBd
serial rate. The receive full/half speed control is used to set the receive path of a channel to either a 2.125 GBd serial rate (when set to logic one) or a
1.0625 GBd serial rate. If RX Byte Align Enable (register 24, bit 1) is set (1), then setting Enable Comma Edge Align will cause the recovered clock output
for this channel to be aligned such that the comma characters from an ordered set will be always be clocked on the positive edge of RCn (when Comma
Edge Alignment is 1), or the negative edge of RCn (when Comma Edge Alignment is 0). Note that this should only be used if the spacing of comma
containing control codes is appropriate, as for example in Fibre Channel code sets. The enable loopback bit causes the high speed serial data output to be
looped back internally to the high speed deserializer if the bit is set to logic one. This causes the data input to the high-speed input to be ignored. Bit 10
causes the RX PLL loss of CDR (clock data recovery) lock bit to be included in the LOSn signal. The default is that LOSn is determined solely by signal
amplitude detection on the serial data inputs.
Reg 19
15
14:6
5:0
9 Bit Error Code (common)
Reserved
Nine Bit Error Code[8:0]
Reserved
Default
0
9’h1FE
6’h00
Mode
Reserved RW
RW
Reserved RW
Register 19 is only applicable in codec mode (PMX=1) and contains the error code output by the 8B/10B decoder when an invalid code or disparity error is
detected. When this occurs, pins RDA[8:0] will contain the nine bit error code, and RDA[9] will be asserted to one. On the transmit side, if an invalid K code
is clocked into the TDA[9:0] pins, the nine bit error code will be encoded and transmitted. This is a common register: data written to channel A is used for
all channels.
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