HDMP-2689 Datasheet, PDF (4/28 Pages) Agilent(Hewlett-Packard) – Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes

For half rate operation, the data
is input in single data rate (SDR)
mode. For SDR each parallel
input data word is clocked in on
the falling edge of the input
transmit byte clock (TC[A-D]).
The timing requirements are
specified in Figure 9 Case A. For
full rate operation, the data must
be input in double data rate
(DDR) mode, with one data word
input on the rising edge of the
input transmit byte clock
(TC[A-D]) and the next word on
the falling edge. Two data words
are input every transmit byte
clock cycle. The timing require-
ments for DDR operation are
shown in Figure 9 Case B.
TC[A-D] always operates at
106.25 MHz.
The default settings for the
HDMP-2689 are full rate opera-
tion and DDR.
Serial Data Outputs
Through AC coupling, the high-
speed outputs are capable of
interfacing directly to copper
cables or PCB traces for electri-
cal transmission or to a separate
fiber optic module for optical
transmission (see Figure 5).
These outputs include user-
controllable skin-loss equaliza-
tion and amplitude control to
improve performance when
driving copper lines. In normal
operation, the serialized
TDn[9:0] data is placed at
TXnP/N. The output drivers
provide for controllable pre-
emphasis and amplitude settings
by programming management
interface register 26 (see Fig-
ure 6). If pre-emphasis is used,
0 →1 and 1→ 0 transitions on
TXnP/N have greater amplitude
than 0 → 0 and 1 → 1 transitions.
This increased amplitude coun-
teracts the effects of skin loss
and dispersion on long PCB
transmission lines. The serial
outputs can also be disabled
through register 26.
VDDA
HS_OUT
50 Ω
50 Ω
FROM
CORE
of
CHIP
VDDA
VDDA
TXnP
0.01 µF
Z₀=50 Ω
RXnP
0.01 µF
TXnN
Z₀=50 Ω
RXnN
HS_IN
VDDA
100 Ω
TO
CORE
of
CHIP
GNDA
ESD
PROTECTION
GNDA
GNDA
ESD
PROTECTION
GNDA
Notes: HS_IN inputs should never be connected to ground as permanent damage to the device may result.
Capacitors may be placed at the sending or receiving end.
Figure 5. High Speed Input and Output Configurations.
Peak[2:0]=0
V_DIFF=V_TXP-VTXN
Peaking Levels
Peak[2:0]=7
V_{PEAK_STATIC}
V_PEAK
V_SUSTAIN
Note: The peaked value at the transition edge does not reach to VPEAK_STATIC value because of the reflection
between driver and package. The static value can be measured as the final value of a long (longer than 2 bits)
1 or 0 pulse with zero peaking.
Figure 6. High Speed Output Pre-Emphasis.
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