HD66766R Datasheet, PDF (93/97 Pages) Hitachi Semiconductor – 132 x 176-dot Graphics LCD Controller/Driver for 65K Colors

HD66766R
80-system Bus Operation
Rev. 1.0-1 / September 2002
RS
CS*
WR *
RD*
VIH
VIL
tAS
VIH
VIL
tAH
VIH
VIL
Note 1)
PWLW, PWLR
PWHW, PWHR
VIH
VIH
VIL
VIL
tWRr
tCYCW, tCYCR
tWRf
DB0
to DB15
tDDR
tDSW
tHWR
VIH _{Wrire data}
VIH
VIL
VIL
tDHR
DB0
to DB15
VOH1 _{Read data}
VOL1
VOH1
VOL1
Figure 80 80-system Bus Timing
Note1) PWLW and PWLR are specified in the overlapped period when CS* is low and WR* or RD* is
low.
Note2) Parallel data transfer is enabled on the DB15-0 pins when the 8-bit bus interface is used. Fix the
DB7-0 pins to Vcc or GND.
93