HD66766R Datasheet, PDF (92/97 Pages) Hitachi Semiconductor – 132 x 176-dot Graphics LCD Controller/Driver for 65K Colors

HD66766R
Timing Characteristics
68-system Bus Operation
Rev. 1.0-1 / September 2002
RS
R/W
CS*
E
Note2)
DB0
to DB15
Note 2)
DB0
to DB15
VIH
VIL
tASE
VIH
VIL
tAHE
VIL
VIL
Note 1)
PWEH
PWEL
VIH
VIH
VIL
VIL
VIL
tEr
tEf
t DSWE
tCYCE
t^HE
VIH
VIH
VIL ^{Wrire data}
VIL
tDDRE
tDHRE
VOH1
Read data
VOL1
VOH1
VOL1
Figure79 68-system Bus Timing
Notes: 1) PWEH is specified in the overlapped period when CS* is low and E is high.
2) Parallel data transfer is enabled on the DB15-8 pins when the 8-bit bus interface is used.
Fix the DB7-0 pins to Vcc or GND.
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