HD66766R Datasheet, PDF (43/97 Pages) Hitachi Semiconductor – 132 x 176-dot Graphics LCD Controller/Driver for 65K Colors

HD66766R
Rev. 1.0-1 / September 2002
Serial Data Transfer
Setting the IM2 pin to the “Vcc” level and the IM1 pin to the “GND” level allows standard clock-
synchronized serial data transfer, using the chip select line (CS*), serial transfer clock line (SCL), serial
input data line (SDI), and serial output data line (SDO). For a serial interface, the IM0/ID pin function
uses an ID pin. If the chip is set up for serial interface, the DB15-2 pins which are not used must be
fixed at “Vcc” or “GND”.
The HD66766R initiates serial data transfer by transferring the start byte at the falling edge of CS* input.
It ends serial data transfer at the rising edge of CS* input.
The HD66766R is selected when the 6-bit chip address in the start byte transferred from the transmitting
device matches the 6-bit device identification code assigned to the HD66766R. The HD66766R, when
selected, receives the subsequent data string. The least significant bit of the identification code can be
determined by the ID pin. The five upper bits must be “01110”. Two different chip addresses must be
assigned to a single HD66766R because the seventh bit of the start byte is used as a register select bit
(RS): that is, when RS = “0”, data can be written to the index register or status can be read, and when RS
= “1”, an instruction can be issued or data can be written to or read from RAM. Read or write is selected
according to the eighth bit of the start byte (R/W bit). The data is received when the R/W bit is “0”, and is
transmitted when the R/W bit is “1”.
After receiving the start byte, the HD66766R receives or transmits the subsequent data byte-by-byte.
The data is transferred with the MSB first. All HD66766R instructions are 16 bits. Two bytes are received
with the MSB first (DB15 to 0), then the instructions are internally executed. After the start byte has been
received, the first byte is fetched internally as the upper eight bits of the instruction and the second byte is
fetched internally as the lower eight bits of the instruction.
Five bytes of RAM read data after the start byte are invalid. The HD66766R starts to read correct RAM
data from the sixth byte.
Table 28 Start Byte Format
Transfer Bit
S
Start byte format
Transfer start
Note: The IM0/ID pin selects ID bit.
1
2
3
4
5
6
7
8
Device ID code
RS R/W
0
1
1
1
0 ID
Table 29 RS and R/W Bit Function
RS R/W
Function
0
0
Sets index register
0
1
Reads status
1
0
Writes instruction or RAM data
1
1
Reads RAM data
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