HD66766R Datasheet, PDF (36/97 Pages) Hitachi Semiconductor – 132 x 176-dot Graphics LCD Controller/Driver for 65K Colors

HD66766R
Rev. 1.0-1 / September 2002
Read Data from GRAM (R22h)
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R 1 ^{RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0}
Figure 24 Read Data from GRAM Instruction
RD15–0: Read 16-bit data from the GRAM. When the data is read to the microcomputer, the first-word
read immediately after the GRAM address setting is latched from the GRAM to the internal read-data
latch. The data on the data bus (DB15–0) becomes invalid and the second-word read is normal.
Sets the I/D, AM,
HSA/HSE, VSA/VEA
Sets the I/D, AM,
HSA/HSE, VSA/VEA
Address: N set
Address: N set
First word
Dummy read (invalid data)
GRAM => Read data latch
First word
Dummy read (invalid data)
GRAM => Read data latch
Second words
Read (data of address N)
Read-data latch => DB11-0
Address: M set
Second words ^{Write (data of address N)}
DB11-0 = > GRAM
Automatic address update: N+
First word
Dummy read (invalid data)
GRAM => Read data latch
Read (data of address N)
Second words _{Read-data latch => DB11-0}
First word
Dummy read (invalid data)
GRAM => Read data latch
Second words
Write (data of address N)
DB11-0 => GRAM
i) Data read to the microcomputer
ii) Logical operation processing
in the HD66766R
Figure 25 GRAM Read Sequence
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