HD66766R Datasheet, PDF (45/97 Pages) Hitachi Semiconductor – 132 x 176-dot Graphics LCD Controller/Driver for 65K Colors

HD66766R
C) Transfer data read from GRAM
CS*
(input)
SCL
(input)
SDI
(input)
Start byte
RS="1"
R/W="1"
Rev. 1.0-1 / September 2002
SDO
(output)
"Start"
Dummy
read (1)
Dummy
read (2)
Dummy
read (3)
Dummy
read (4)
Dummy
read (5)
RAM read RAM read
upper 8-bit lower 8-bit
Five bytes invalid dummy data are read after start byte.
6th data is valid from GRAM.
"End"
Figure 31 Procedure for transfer through the clock synchronized serial interface (c)
d) Status Read / Instruction Read
CS*
(input)
SCL
(input)
SDI
(input)
Start byte
RS="0"
R/W="1"
SDO
(output)
Dummy
read (1)
Status read
upper 8-bit
Status read
lower 8-bit
"Start"
"End"
One byte invalid dummy data are read after start byte.
2nd data is valid from GRAM.
Figure 32 Procedure for transfer through the clock synchronized serial interface (d)
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