HD66766R Datasheet, PDF (33/97 Pages) Hitachi Semiconductor – 132 x 176-dot Graphics LCD Controller/Driver for 65K Colors

HD66766R
0000h
VSA
HSA
Rev. 1.0-1 / September 2002
HEA
VEA
Window Address
Window address setting range:
"00"h HSA7-0 HEA7-0
"00"h VSA7-0 VEA7-0
"83"h
"AF"h
GRAM Address space
AF83h
Figure 19 Window Address Setting Range
Note:
1. Ensure that the window address area is within the GRAM address space.
2. In high-speed write mode, data are written to GRAM in four-words.
Thus, dummy write operations should be inserted depending on the window address
area. For details, see the High-Speed Burst RAM Write Function section.
RAM Write Data Mask (R20h)
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB DB3 DB2 DB1 DB0
W 1 WM15 WM14 WM13 WM12 WM11 WM10 WM9 WM8 WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0
Figure 20 RAM Write Data Mask Instruction
WM15–0: In writing to the GRAM, these bits mask writing in a bit unit. When WM15 = “1”, this bit
masks the write data of DB11 and does not write to the GRAM. Similarly, the WM10 to 0 bits mask the
write data of DB15 to 0 in a bit unit. When HDZ = “1”, mask processing is performed for 12-bit data
after dither processing. For details, see the Write Data Mask Function section.
RAM Address Set (R21h)
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
W
1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Figure 21 RAM Address Set Instruction
AD15–0: Initially set GRAM addresses to the address counter (AC). Once the GRAM data is written,
the AC is automatically updated according to the AM and I/D bit settings. This allows consecutive
accesses without resetting addresses. Once the GRAM data is read, the AC is not automatically updated.
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