HD66717 Datasheet, PDF (48/90 Pages) Hitachi Semiconductor – (Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver)

HD66717
Interface with a 4-Bit MPU
Four-bit data can be transferred in parallel by setting both the IM1 and IM0 pins to the V_CC level (Figure
26). Four-bit data representing higher or lower bits of 8-bit instructions or 8-bit RAM data can be
transferred in that order.
The HD66717 can forcibly reset the counter that counts the number of higher and lower 4-bit data
transfers in a 4-bit bus interface. This function, called transfer-syncronization, can be performed by
writing a special instruction containing 0000 four consecutive times (Figure 27). For example, when a
data transfer sequence becomes disordered due to noise or some undesired factor, this function resets the
counter and thus enables resuming data transfer from the higher 4 bits. Using this function at specified
intervals prevents display-system crash.
RS
R/W
Internal operation
E
Internal signal
DB7
IR7 IR3
Instruction write
Busy AC3
Busy flag check
Not
Busy AC3
Busy flag check
D7 D3
Instruction write
Figure 26 4-Bit Parallel Data Transfer Timing Sequence
RS
R/W
E
DB7–
DB0
0000
(1)
0000
(2)
0000
(3)
0000 ^Higher
Lower
(4)
(4-bit data transfer synchronized)
Figure 27 4-Bit Data Transfer Synchronization
500