HD66717 Datasheet, PDF (39/90 Pages) Hitachi Semiconductor – (Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver)

HD66717
Table 17 Instruction List
Instruction No. R/W RS
Status
SR 1 0
Clear
display
CL 0 0
Return
home
CH 0 0
Start
OS 0 0
oscillator
Entry
EM 0 0
mode set
Cursor
control
CR 0 0
Display
on/off
control
Power
control
DO 0 0
PW 0 0
Display
control
DC 0 0
Contrast CN 0 0
control
Scroll
control
SC 0 0
Annunciator AS 0 0
/SEGRAM
address set
CGRAM CA 0 0
address set
DDRAM DA 0 0
address set
(upper bits)
DDRAM DA 0 0
address set
(lower bits)
Code
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
Execution
Cycle *¹
BF AC AC AC AC AC AC AC Reads busy flag (BF),
0
which indicates internal
operations are being
performed, and reads
address counter (AC).
0 0 0 0 0 0 0 1 Clears entire display and 310
sets DDRAM address 0 in
address counter.
0 0 0 0 0 0 1 0 Sets DDRAM address 0 in 10
address counter.
0 0 0 0 0 0 1 1 Starts oscillation during —
standby mode.
0 0 0 0 0 1 I/D OSC Sets address update
10
direction after RAM access
(I/D), and system clock
division (OSC).
0 0 0 0 1 B/W C B Sets black-white inverting 10
cursor (B/W), 8th raster-
row cursor (C), and blink
cursor (B).
0 0 0 1 0 DC DS LC Sets character display
10
on/off (DC), segment
display on/off (DS), and
line-cursor on/off (LC).
0 0 0 1 1 AMP SLP STB Turns on voltage-follower 10
and booster (AMP), and
sets sleep mode (SLP) and
standby mode (STB).
0 0 1 NL1 NL0 DL3 DL2 DL1 Sets the number of display 10
lines (NL) and the line to be
doubled in height.
0 1 0 SN2 CT3 CT2 CT1 CT0 Sets the display-start line 10
(SN2) and contrast-
adjusting value (CT).
0 1 1 SN1 SN0 SL2 SL1 SL0 Sets the display-start line 10
(SN) and display-start
raster-row (SL).
1 0 0 DA AAN/ AAN/ AAN/ AAN/ Turns on annunciator
10
A_SEG3 A_SEG2 A_SEG1 A_SEG0 display and sets
annunciator/SEGRAM
address.
1
0
1
A_CG4 A_CG3 A_CG2 A_CG1 A_CG0 Sets the initial CGRAM
10
address to the address
counter.
1
1
0
0
0
0
A_DD6 A_DD5 Sets the initial higher
10
DDRAM address to the
address counter.
1
1
1
A_DD4 A_DD3 A_DD2 A_DD1 A_DD0 Sets the initial lower
10
DDRAM address to the
address counter.
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