HD66717 Datasheet, PDF (15/90 Pages) Hitachi Semiconductor – (Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver)

HD66717
Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM, CGRAM, and SEGRAM. RAM read timing for display and internal operation timing
by MPU access are generated separately to avoid interfering with each other. Therefore, when writing
data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas
other than the display area.
Cursor/Blink Control Circuit
The cursor/blink (or white-black inversion) control is used to produce a cursor or a flashing area on the
display at a position corresponding to the location stored in the address counter (AC).
For example (Figure 2), when the address counter is 08H, a cursor is displayed at a position
corresponding to DDRAM address (08)H.
Multiplexing Liquid Crystal Display Driver Circuit
The multiplexing liquid crystal display driver circuit consists of 34 common signal drivers (COM1 to
COM32, COMS1, COMS2) and 60 segment signal drivers (SEG1 to SEG60). When the number of lines
are selected by a program, the required common signal drivers automatically output drive waveforms,
while the other common signal drivers continue to output deselection waveforms.
Character pattern data is sent serially through a 60-bit shift register and latched when all needed data has
arrived. The latched data then enables the segment signal drivers to generate drive waveform outputs.
The shift direction of 60-bit data can be selected by the SFT pin; select the direction appropriate to the
device mounting configuration.
When multiplexing drive is not used, or during standby or sleep mode, all common and segment signal
drivers output the V_CC level, halting display.
Annunciator Driver Circuit
The static annunciator drivers, which are specially used for displaying icons and marks, consists of 1
common signal driver (ACOM) and 10 segment signal drivers (ASEG1 to ASEG10). Since this driver
circuit operates at the logic operating voltage (V_CC–AGND), the LCD drive power supply circuit is not
necessary, and low-power consumption can be achieved. It is suitable for mark indication during system
standby because of its drive capability during standby and sleep modes. When multiplexing drive is not
used, or during standby or sleep mode, all common and segment signal drivers output the V_CC level,
halting display.
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