HD66717 Datasheet, PDF (4/90 Pages) Hitachi Semiconductor – (Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver)

HD66717
LCD-II Family Comparison (cont)
Item
HD66720
Power supply voltage
2.7V to 5.5V
Liquid crystal drive voltage 3.0 to 11.0V
Maximum display
characters per chip
10 characters ×
1 line/
8 characters ×
2 lines
Segment display
42 (extended to 80)
Display duty ratio
1/9 and 1/17
CGROM
9,600 bits
(240 5-×-8 dot
characters)
CGRAM
64 bytes
DDRAM
40 bytes
SEGRAM
16 bytes
Segment signals
42
Common signals
17
Liquid crystal drive
B
waveform
Clock source
External resistor
or external clock
Rf oscillation frequency 160 kHz ± 30%
Liquid crystal voltage
booster circuit
Liquid crystal drive
operational amplifier
Bleeder-resistor for liquid
crystal drive
Liquid crystal contrast
adjuster
Key scan circuit
Extension driver control
signal
Reset function
Horizontal smooth scroll
Vertical smooth scroll
Number of displayed lines
Low power control
Bus interface
Package
Double or triple
booster circuit
None
External
None
5 × 6 = 30 keys
Independent
control signal
Internal reset
circuit or reset input
Dot unit and
line unit
Impossible
1 or 2
Low power mode and sleep
mode
Serial
100-pin QFP1420
100-pin TQFP1414
100-pin bare chip
HD66717
2.4V to 5.5V
3.0 to 13.0V
12 characters ×
1 line/2 lines/3 lines/4 lines
40 (and 10 annunciators)
1/10, 1/18, 1/26, and 1/34
9,600 bits
(240 5-×-8 dot
characters)
32 bytes
60 bytes
8 bytes
60
34
B
External resistor
or external clock
1-line mode: 40 kHz ± 30%
2-line mode: 80 kHz ± 30%
3-line mode: 120 kHz ± 30%
4-line mode: 160 kHz ± 30%
Double or triple
booster circuit
Built-in for each V1 to V5
Internal 1/4 and 1/6 bias
resistors
Incorporated
None
None
Reset input
Impossible
Dot (raster-row) unit
1, 2, 3, or 4
Standby mode and
sleep mode
I²C, serial, 4, or 8 bits
Slim chip with/without bumps
TCP
HD66727
2.4V to 5.5V
3.0 to 13.0V
12 characters ×
1 line/2 lines/3 lines/4 lines
40 (and 12 annunciators)
1/10, 1/18, 1/26, and 1/34
11,520 bits
(240 6-×-8 dot
characters)
32 bytes
60 bytes
8 bytes
60
34
B
External resistor
or external clock
1-line mode: 40 kHz ± 30%
2-line mode: 80 kHz ± 30%
3-line mode: 120 kHz ± 30%
4-line mode: 160 kHz ± 30%
Double or triple
booster circuit
Built-in for each V1 to V5
Internal 1/4 and 1/6 bias
resistors
Incorporated
4 × 8 = 32 keys
None
Reset input
Impossible
Dot (raster-row) unit
1, 2, 3, or 4
Standby mode and
sleep mode
I²C or clock-synchronized serial
Slim chip with/without bumps
TCP
455