HD66717 Datasheet, PDF (12/90 Pages) Hitachi Semiconductor – (Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver)

HD66717
Block Function Description
System Interface
The HD66717 has four types of system interfaces: I²C bus, clock-synchronized serial, 4-bit bus, and 8-bit
bus. The interface mode is selected by the IM1 and IM0 pins.
The HD66717 has two 8-bit registers: an instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear, return home, and display control, and address
information for the display data RAM (DDRAM), the character generator RAM (CGRAM), and the
segment RAM (SEGRAM). The IR can only be written to by MPU and cannot be read from.
The DR temporarily stores data to be written into DDRAM, CGRAM, SEGRAM, or annunciator. Data
written into the DR from the MPU is automatically written into DDRAM, CGRAM, SEGRAM, or
annunciator by an internal operation. The DR is also used for data storage when reading data from
DDRAM, CGRAM, or SEGRAM. When address information is written into the IR, data is read and then
stored into the DR from DDRAM, CGRAM, or SEGRAM by an internal operation. Data transfer between
the MPU is then completed when the MPU reads the DR. After the read, data in DDRAM, CGRAM, or
SEGRAM at the next address is sent to the DR for the next read from the MPU.
These two registers can be selected by the register select (RS) signal in the 4/8-bit bus interface, and by
the RS bit in I²C bus or clock-synchronized serial interface (Table 2).
Busy Flag (BF)
When the busy flag is 1, the HD66717 is in the internal operation mode, and the next instruction will not
be accepted. When RS = low and R/W = high in 4/8-bit bus mode (Table 2), the busy flag is output from
DB7. The next instruction must be written after ensuring that the busy flag is 0. The busy flag cannot be
read in I²C bus mode or clock-synchronized serial mode; data must be transferred in appropriate timing
considering instruction execution times.
Address Counter (AC)
The address counter (AC) assigns addresses to DDRAM, CGRAM, or SEGRAM. When the address set
instruction is written into the IR, the address information is sent from the IR to the AC. Selection of
DDRAM, CGRAM, and SEGRAM is also determined concurrently by the instruction.
After writing into (reading from) DDRAM, CGRAM, or SEGRAM, the AC is automatically incremented
by 1 (or decremented by 1). The AC contents are then output to DB0 to DB6 when RS = low and R/W =
high in 4/8-bit bus mode (Table 2).
463