HD66717 Datasheet, PDF (37/90 Pages) Hitachi Semiconductor – (Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver)

HD66717
DDRAM Address Set
The DDRAM address set instruction (Figure 19) includes the A bits.
AAAAAAA: Used for setting the DDRAM address in the address counter (AC). The DDRAM addresses
range from 00H to 4BH (60 addresses) (Table 16).
Once the DDRAM address is set, data in the DDRAM can be accessed consecutively since the address
counter is automatically incremented or decremented according to the I/D bit setting after each access.
Here, invalid addresses are automatically skipped. The DDRAM address cannot be set during sleep or
standby mode.
RS R/W DB7
DB0
0 0 1 1 0 0 0 0 A A Upper bits
0 0 1 1 1 A A A A A Lower bits
Figure 19 DDRAM Address Set Instruction
Table 16 DDRAM Addresses and Invalid Addresses
Displayed Line
1st line
2nd line
3rd line
4th line
5th line
DDRAM Address
00H to 0BH
10H to 1BH
20H to 2BH
30H to 3BH
40H to 4BH
Invalid Addresses
0CH to 0FH
1CH to 1FH
2CH to 2FH
3CH to 3FH
4CH and subsequent addresses
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