HD66717 Datasheet, PDF (40/90 Pages) Hitachi Semiconductor – (Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver)

HD66717
Table 17 Instruction List (cont)
Code
Instruction No. R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
Execution
Cycle *¹
Write data WD 0 1
to RAM
Write data
Writes data to DDRAM, 10
CGRAM, SEGRAM, or
annunciator.
Read data RD 1 1
from RAM
Read data
Reads data from DDRAM, 10
CGRAM, or SEGRAM.
Note:
BF = 1: Internally operating
AC: Address counter
I/D = 1: Increment
I/D = 0: Decrement
OSC = 1: System clock divided by four
B/W = 1: Black-white inverting cursor on
C = 1: 8th raster-row cursor on
B = 1: Blink cursor on
D = 1: Display on
DC = 1: Character display on
DS = 1: Segment display on
LC = 1: Line containing AC given cursor attribute
AMP = 1: Voltage-follower and booster on
SLP = 1: Sleep mode
STB = 1: Standby mode
NL1,NL0: Number of display lines [00: 1line (1/10 duty ratio), 01: 2 lines (1/18 duty ratio),
10: 3 lines (1/26 duty ratio),11:4 lines (1/34 duty ratio)]
DL3 – DL1: Double-height lines (DL1 = 1: 1st line, DL2 = 1: 2nd line, DL3 = 1: 3rd line)
CT3–CT0: Contrast adjustment
SN2 – SN0: Display-start line (000: 1st line, 001: 2nd line, 010: 3rd line, 011: 4th line, 100: 5th line)
SL2 – SL0: Display-start raster-row (000: 1st raster-row... 111: 8th raster-row)
DA = 1: Annunciator display on
AAN/A_SEG = 0000–0010: Annunciator address
ACG4–ACG0: CGRAM address (00000–11111)
AAN/A_SEG = 1000–1111: SEGRAM address
ADD6–ADD0: DDRAM address (0000000–1001011)
1. Represented by the number of operating clock pulses; the execution time depends on the
supplied clock frequency or the internal oscillation frequency.
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