HD66717 Datasheet, PDF (13/90 Pages) Hitachi Semiconductor – (Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver)

HD66717
Table 2 Register Selection
RS
R/W Operation
0
0
IR write as an internal operation (display clear, etc.)
0
1
Read busy flag (DB7) read and address counter (DB0 to DB6) (4/8-bit bus interface)
1
0
DR write as an internal operation (DR to DDRAM, CGRAM, SEGRAM, or annunciator)
1
1
DR read as an internal operation (DDRAM, CGRAM, or SEGRAM to DR)
(4/8-bit bus interface)
Display Data RAM (DDRAM)
Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its capacity is 60 ×
8 bits, or 60 characters, which is equivalent to an area of 12 characters × 5 lines. Any number of display
lines (LCD drive duty ratio) from 1 to 4 can be selected by software. Here, assignment of DDRAM
addresses is the same for all display modes (Table 3). The line to be displayed at the top of the display
(display-start line) can also be selected by register settings. See Table 4.
Address
counter
(AC)
MSB
LSB
AC 6 AC5 AC4 AC3 AC2 AC1 AC0
Example : DDRAM address 4A
1 001 0 1 0
Figure 1 Address Counter and DDRAM Address
Table 3 DDRAM Addresses and Display Positions
Display
Line
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th
Char. Char. Char. Char. Char. Char. Char. Char. Char. Char. Char. Char.
1st
00 01 02 03 04 05 06 07 08 09 0A 0B
2nd
10 11 12 13 14 15 16 17 18 19 1A 1B
3rd
20 21 22 23 24 25 26 27 28 29 2A 2B
4th
30 31 32 33 34 35 36 37 38 39 3A 3B
5th
40 41 42 43 44 45 46 47 48 49 4A 4B
Note: Char. indicates character position.
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