MB82DBS02163C Datasheet, PDF (9/63 Pages) Fujitsu Component Limited. – 32 M Bit (2 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS02163C-70L
• Power Down
The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode
and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from power down
mode.
This device has 3 power down modes, Sleep, 4 M-bit Partial, and 8 M-bit Partial.
The selection of power down mode is set through CR set sequence. Each mode has following data retention
features.
Mode
Sleep [default]
4 M-bit Partial
8 M-bit Partial
Data Retention Size
No
4 M bits
8 M bits
Retention Address
N/A
000000h to 03FFFFh
000000h to 07FFFFh
The default state after power-up is Sleep and it is the lowest power consumption but all data will be lost once
CE2 is brought to Low for Power Down. It is not required to perform CR set sequence to set to Sleep mode after
power-up in case of asynchronous operation.
• Burst Read/Write Operation
Synchronous burst read/write operation provides faster memory access that synchronized to microcontroller or
system bus frequency. Configuration Register(CR) Set is required to perform burst read & write operation after
power-up. Once CR set sequence is performed to select synchronous burst mode, the device is configured to
synchronous burst read/write operation mode with corresponding RL and BL that is set through CR set sequence
together with operation mode. In order to perform synchronous burst read & write operation, it is required to
control new signals, CLK, ADV and WAIT that Low Power SRAMs do not have.
• Burst Read Operation
CLK
Address
ADV
CE1
Valid address
OE
WE
DQ
WAIT
High
RL
High-Z
High-Z
Q1
Q2
QBL
BL
(Continued)
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