MB82DBS02163C Datasheet, PDF (7/63 Pages) Fujitsu Component Limited. – 32 M Bit (2 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS02163C-70L
■ FUNCTIONAL DESCRIPTION
This device supports asynchronous read, page read & normal write operation and synchronous burst read and
burst write operation for faster memory access and features 3 kinds of power down modes for power saving as
user configurable option.
• Power-up
It is required to follow the power-up timing to start executing proper device operation. Refer to "Power-up Timing".
After Power-up, the device defaults to asynchronous page read & normal write operation mode with sleep power
down feature.
• Configuration Register
The Configuration Register(CR) is used to configure the type of device function among optional features. Each
selection of features is set through CR set sequence after power-up. If CR set sequence is not performed after
power-up, the device is configured for asynchronous operation with sleep power down feature as default con-
figuration.
• CR Set Sequence
The CR set requires total 6 read/write cycles with unique address. Operation other than read/write operation
requires that device being in standby mode. Following table shows the detail sequence.
Cycle #
#1
#2
#3
#4
#5
#6
Operation
Read
Write
Write
Write
Write
Read
Address
1FFFFFh (MSB)
1FFFFFh
1FFFFFh
1FFFFFh
1FFFFFh
Address Key
Data
Read Data (RDa)
RDa
RDa
X
X
Read Data (RDb)
The first cycle is to read from most significant address(MSB).
The second and third cycles are to write to MSB. If the second or third cycle is written into the different address,
the CR set is cancelled and the data written by the second or third cycle is valid as a normal write operation. It
is recommended to write back the data(RDa) read by first cycle to MSB in order to secure the data.
The forth and fifth cycles are to write to MSB. The data of forth and fifth cycle is don't-care. If the forth or fifth
cycle is written into different address, the CR set is also cancelled, but write data may not be written as normal
write operation.
The last cycle is to read from specific address key for mode selection. And read data(RDb) is invalid.
Once this CR set sequence is performed from an initial CR set to the other new CR set, the written data stored
in memory cell array may be lost. So, it should perform the CR set sequence prior to regular read/write operation
if necessary to change from default configuration.
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