MB82DBS02163C Datasheet, PDF (11/63 Pages) Fujitsu Component Limited. – 32 M Bit (2 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS02163C-70L
• WAIT Output Function
The WAIT is output signal to indicate data bus status when the device is operating in synchronous burst mode.
During burst read operation, WAIT output is enabled after specified time duration from OE = L or CE1 = L
whichever occurs last. WAIT output Low indicates data output at next clock cycle is invalid, and WAIT output
becomes High one clock cycle prior to valid data output. During continuous burst read operation, an additional
output delay may occur when a burst sequence crosses it's device-row boundary. The WAIT output notifies this
delay to controller. Refer to the section "Burst Length" for the additional delay cycles in details. During OE read
suspend, WAIT output does not indicate data bus status but carries the same level from previous clock cycle
(kept High) except for read suspend on the final data output. If final read data output is suspended, WAIT output
becomes high impedance after specified time duration from OE = H.
During burst write operation, WAIT output is enabled to High level after specified time duration from WE = L or
CE1 = L whichever occurs last and kept High for entire write cycles including WE write suspend. The actual
write data latching starts on the appropriate clock edge with respect to Valid Clock Edge, Read Latency, and
Burst Length. During WE Write suspend, WAIT output does not indicate data bus status but carries the same
level from previous clock cycle (kept High) except for write suspend on the final data input. If final write data
input is suspended, WAIT output becomes high impedance after specified time duration from WE = H.
The burst operation is always started after fixed latency with respect to Read Latency set in CR.
When the device is operating in asynchronous mode, WAIT output is always in High Impedance.
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