MB82DBS02163C Datasheet, PDF (24/63 Pages) Fujitsu Component Limited. – 32 M Bit (2 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS02163C-70L
(6) Synchronous Write Operation (Burst mode)
(At recommended operating conditions unless otherwise noted)
Parameter
Symbol
Value
Min
Max
Unit Notes
Burst Write Cycle Time
tWCB
⎯
8000
ns
Data Setup Time to CLK
tDSCK
7
⎯
ns
Data Hold Time from CLK
tDHCK
3
⎯
ns
WE Low Setup Time to 1st Data Input
tWLD
30
⎯
ns
LB, UB Setup Time for Write
tBS
-5
⎯
ns *1
WE Setup Time to CLK
tWSCK
5
⎯
ns
WE Hold Time from CLK
tCKWH
5
⎯
ns
CE1 Low to WAIT High
tCLTH
5
20
ns *2
WE Low to WAIT High
tWLTH
0
20
ns *2
CE1 High to WAIT High-Z
tCHTZ
⎯
20
ns *2
WE High to WAIT High-Z
tWHTZ
⎯
20
ns *2
Burst End CE1 Low Hold Time from CLK
tCKCLH
5
⎯
ns
Burst End CE1 High Setup Time to next CLK
tCHCK
5
⎯
ns
Burst End LB, UB Hold Time from CLK
tCKBH
5
⎯
ns
Burst Write Recovery Time
tWRB
30
⎯
ns *3
Burst Terminate
Recovery Time
BL = 8, 16
30
tTRB
BL = Continuous
70
⎯
ns *4
⎯
ns *4
*1: Defined from the valid input edge to the High to Low transition of either ADV, CE1, or WE, whichever occurs
last. And once LB, UB are determined, LB, UB must not be changed until the end of burst write.
*2: The output load 50 pF with 50 Ω termination to VDD × 0.5 V.
*3: Defined from the valid clock edge where last data-input being latched at the end of burst write to the High to
Low transition of either ADV or CE1 whichever occurs late for the next access.
*4: Defined from the Low to High transition of CE1 to the High to Low transition of either ADV or CE1 whichever
occurs late for the next access.
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