MB82DBS02163C Datasheet, PDF (22/63 Pages) Fujitsu Component Limited. – 32 M Bit (2 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS02163C-70L
(3) Synchronous Operation - Clock Input (Burst mode)
(At recommended operating conditions unless otherwise noted)
Parameter
Symbol
Value
Min
Max
Unit Notes
RL = 5
15
⎯
ns *1
Clock Period
RL = 4
tCK
20
⎯
ns *1
RL = 3
30
⎯
ns *1
Clock High Pulse Width
tCKH
5
⎯
ns
Clock Low Pulse Width
tCKL
5
⎯
ns
Clock Transition Time
tCKT
⎯
3
ns *2
*1: Clock period is defined between valid clock edges.
*2: Clock transition time is defined between VIH (Min) and VIL (Max)
(4) Synchronous Operation - Address Latch (Burst mode)
(At recommended operating conditions unless otherwise noted)
Parameter
Symbol
Value
Min
Max
Unit Notes
Address Setup Time to CE1 Low
tASCL
−5
⎯
ns *1
Address Setup Time to ADV Low
tASVL
−5
⎯
ns *2
Address Hold Time from ADV High
tAHV
10
⎯
ns
ADV Low Pulse Width
tVPL
10
⎯
ns *3
ADV Low Setup Time to CLK
tVSCK
7
⎯
ns *4
CE1 Low Setup Time to CLK
tCLCK
7
⎯
ns *4
ADV Low Hold Time from CLK
tCKVH
1
⎯
ns *4
Burst End ADV High Hold Time from CLK
tVHVL
15
⎯
ns
*1: tASCL is applicable if CE1 is brought to Low after ADV is brought to Low.
*2: tASVL is applicable if ADV is brought to Low after CE1 is brought to Low.
*3: tVPL is specified from the falling edge of either CE1 or ADV whichever comes late.
*4: Applicable to the 1st valid clock edge.
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