MB82DBS02163C Datasheet, PDF (10/63 Pages) Fujitsu Component Limited. – 32 M Bit (2 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS02163C-70L
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• Burst Write Operation
CLK
Address
Valid address
ADV
CE1
OE
High
WE
DQ
High-Z
RL-1
WAIT
High-Z
D1
D2
DBL
BL
• CLK Input Function
The CLK is input signal to synchronize memory to microcontroller or system bus frequency during synchronous
burst read & write operation. The CLK input increments device internal address counter and the valid edge of
CLK is referred for latency counts from address latch, burst write data latch, and burst read data output. During
synchronous operation mode, CLK input must be supplied except for standby state and power down state. CLK
is Don't care during asynchronous operation.
• ADV Input Function
The ADV is input signal to latch valid address. It is applicable to synchronous operation as well as asynchronous
operation. ADV input is active during CE1 = L and CE1 = H disables ADV input. All addresses are determined
on the rising edge of ADV.
During synchronous burst read/write operation, ADV = H disables all address inputs. Once ADV is brought to
High after valid address latch, it is inhibited to bring ADV Low until the end of burst or until burst operation is
terminated. ADV Low pulse is mandatory for synchronous burst read/write operation mode to latch the valid
address input.
During asynchronous operation, ADV = H also disables all address inputs. ADV can be tied to Low during
asynchronous operation and it is not necessary to control ADV to High.
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