MB82DBS04163C Datasheet, PDF (4/62 Pages) Fujitsu Component Limited. – MEMORY Mobile FCRAMTM CMOS 64 M Bit (4 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS04163C-70L
2. Synchronous Operation (Burst Mode)
Mode
CE2 CE1 CLK ADV WE OE LB UB A21 to A0 DQ8 to DQ1 DQ16 to DQ9 WAIT
Standby(Deselect)
H X X X X X X X High-Z High-Z High-Z
Start Address Latch*¹
X*⁴ X*⁴
*³
Valid*⁷ High-Z*⁸ High-Z*⁸ High-Z*¹¹
Advance Burst Read
to Next Address*¹
*³
L
H
Burst Read
Suspend*¹
L
H
*³
H
X*⁶ X*⁶
Advance Burst Write
to Next Address*¹
H L*⁵
*³
X
H
Burst Write Suspend*¹
H*⁵
*³
Output
Valid*⁹
Output
Valid*⁹
Output
Valid
High-Z High-Z High*¹²
Input
Valid*¹⁰
Input
Invalid
Input
Valid*¹⁰
Input
Invalid
High*¹³
High*¹²
Terminate Burst Read
X
HX
High-Z High-Z High-Z
Terminate Burst Write
X
XH
High-Z High-Z High-Z
Power Down*²
L X X X X X X X X High-Z High-Z High-Z
Note : L = VIL, H = VIH, X can be either VIL or VIH, = valid edge, = rising edge of Low pulse,
High-Z = High impedance
*1 : Should not be kept this logic condition longer than 4 µs.
*2 : Power Down mode can be entered from Standby state and all output are in High-Z state.
Data retention depends on the selection of Partial Size for Power Down Program.
Refer to "Power Down" in “■FUNCTIONAL DESCRIPTION” for the details.
*3 : Valid clock edge shall be set on either rising or falling edge through CR set. CLK must be started and stable
prior to memory access.
*4 : Can be either VIL or VIH except for the case the both of OE and WE are VIL.
It is prohibited to bring the both of OE and WE to VIL.
*5 : When device is operating in "WE Single Clock Pulse Control" mode, WE is don't care once write operation
is determined by WE Low Pulse at the beginning of write access together with address latching. Burst write
suspend feature is not supported in "WE Single Clock Pulse Control" mode.
*6 : Can be either VIL or VIH but must be valid before Read or Write is determined. And once LB and UB input
levels are determined, they must not be changed until the end of burst.
*7 : Once valid address is determined, input address must not be changed during ADV = L.
*8 : If OE = L, output is either Invalid or High-Z depending on the level of LB and UB input. If WE = L, input is
Invalid. If OE = WE = H, output is High-Z.
*9 : Outputs is either Valid or High-Z depending on the level of LB and UB input.
*10 : Input is either Valid or Invalid depending on the level of LB and UB input.
*11 : Output is either High-Z or Invalid depending on the level of OE and WE input.
*12 : Keep the level from previous cycle except for suspending on last data. Refer to "WAIT Output Function" in
"■FUNCTIONAL DESCRIPTION" for the details.
*13 : WAIT output is driven in High level during burst write operation.
4