MB82DBS04163C Datasheet, PDF (3/62 Pages) Fujitsu Component Limited. – MEMORY Mobile FCRAMTM CMOS 64 M Bit (4 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS04163C-70L
■ FUNCTION TRUTH TABLE
1. Asynchronous Operation (Page Mode)
Mode
CE2 CE1 CLK ADV WE OE LB UB A21 to A0 DQ8 to DQ1 DQ16 to DQ9 WAIT
Standby
(Deselect)
HH X X XXXX
X
High-Z High-Z High-Z
Output Disable*¹
X *3 H H X X *5 High-Z High-Z High-Z
Output Disable
(No Read)
X *3
H H Valid High-Z High-Z High-Z
Read (Upper Byte)
X *3
H
L Valid High-Z
Output
Valid
High-Z
Read (Lower Byte)
X
*3
H
L
L
H
Valid
Output
Valid
High-Z High-Z
Read (Word)
H L ^{X *3}
L
L
Valid
Output
Valid
Output
Valid
High-Z
Page Read
X *3
L/H L/H Valid
*6
*6
High-Z
No Write
X *3
H H Valid Invalid Invalid High-Z
Write (Upper Byte)
X *3
H L Valid Invalid Input Valid High-Z
Write (Lower Byte)
X
*3
L H*⁴ _L
H Valid
Input
Valid
Invalid High-Z
Write (Word)
X *3
L
L Valid
Input
Valid
Input Valid High-Z
Power Down*²
LX X X XXXX
X
High-Z High-Z High-Z
Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance
*1 : Should not be kept this logic condition longer than 1 µs.
*2 : Power Down mode can be entered from Standby state and all output are in High-Z state.
Data retention depends on the selection of Partial Size for Power Down Program.
Refer to "Power Down" in "■FUNCTIONAL DESCRIPTION" for the details.
*3 : "L" for address pass through and "H" for address latch on the rising edge of ADV.
*4 : OE can be VIL during write operation if the following conditions are satisfied;
(1) Write pulse is initiated by CE1. See "(14) Asynchronous Read/Write Timing 1-1 (CE1 Control)" in
"■TIMING DIAGRAMS".
(2) OE stays VIL during Write cycle.
*5 : Can be either VIL or VIH but must be valid before Read or Write.
*6 : Output of upper and lower byte data is either Valid or High-Z depending on the level of LB and UB input.
3