MB82DBS04163C Datasheet, PDF (10/62 Pages) Fujitsu Component Limited. – MEMORY Mobile FCRAMTM CMOS 64 M Bit (4 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS04163C-70L
• ADV Input Function
The ADV is input signal to latch valid address. It is applicable to synchronous operation as well as asynchronous
operation. ADV input is active during CE1 = L and CE1 = H disables ADV input. All addresses are determined
on the rising edge of ADV.
During synchronous burst read/write operation, ADV = H disables all address inputs. Once ADV is brought to
High after valid address latch, it is inhibited to bring ADV Low until the end of burst or until burst operation is
terminated. ADV Low pulse is mandatory for synchronous burst read/write operation mode to latch the valid
address input.
During asynchronous operation, ADV = H also disables all address inputs. ADV can be tied to Low during
asynchronous operation and it is not necessary to control ADV to High.
• WAIT Output Function
The WAIT is output signal to indicate data bus status when the device is operating in synchronous burst mode.
During burst read operation, WAIT output is enabled after specified time duration from OE = L or CE1 = L
whichever occurs last. WAIT output Low indicates data output at next clock cycle is invalid, and WAIT output
becomes High one clock cycle prior to valid data output. During OE read suspend, WAIT output doesn’t indicate
data bus status but carries the same level from previous clock cycle (kept High) except for burst read suspend
on the final data output. If final read data output is suspended, WAIT output becomes high impedance after
specified time duration from OE = H.
During burst write operation, WAIT output is valid to High level after specified time duration from WE = L or CE1
= L whichever occurs last and kept High for entire write cycles including WE write suspend. The actual write
data latching starts on the appropriate clock edge with respect to Valid Clock Edge, Read Latency, and Burst
Length. During WE write suspend, WAIT output doesn’t indicate data bus status but carries the same level from
previous clock cycle (kept High) except for write suspend on the final data input. If final write data input is
suspended, WAIT output becomes high impedance after specified time duration from WE = H.
This device doesn’t incur additional output delay against crossing device-row boundary or internal refresh op-
eration. Therefore, the burst operation is always started after fixed latency with respect to read latency. And there
is no waiting cycle asserted in the middle of burst operation except for burst read or write suspend by OE brought
to High or WE brought to High. Thus, once WAIT output is enabled and brought to High, WAIT output keeps
High level until the end of burst or until the burst operation is terminated.
When the device is operating in asynchronous mode, WAIT output is always in High Impedance.
• Latency
Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming
available during synchronous burst read operation. It is set through CR set sequence after power-up. Once
specific RL is set through CR set sequence, write latency, that is the number of clock cycles between address
being latched and first write data being latched, is automatically set to RL-1. The burst operation is always started
after fixed latency with respect to Read Latency set in CR.
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