MB82DBS04163C Datasheet, PDF (12/62 Pages) Fujitsu Component Limited. – MEMORY Mobile FCRAMTM CMOS 64 M Bit (4 M word×16 bit) Mobile Phone Application Specific Memory

MB82DBS04163C-70L
• Address Latch by ADV
The ADV latches valid address presence on address inputs. During synchronous burst read/write operation
mode, all the address are determined on the rising edge of ADV when CE1 = L. The specified minimum value
of ADV = L setup time and hold time against valid edge of clock where RL count is begun must be satisfied.
Valid address must be determined with specified setup time against either the falling edge of ADV or falling edge
of CE1 whichever comes late. And the determined valid address must not be changed during ADV = L period.
• Burst Length
Burst Length is the number of word to be read or written during synchronous burst read/write operation as the
result of a single address latch cycle. It can be set on 8,16 words boundary or continuous for entire address
through CR set sequence. The burst type is sequential that is incremental decoding scheme within a boundary
address. Starting from initial address being latched, device internal address counter assigns +1 to the previous
address until reaching the end of boundary address and then wrap round to least significant address (= 0). After
completing read data output or write data latch for the set burst length, operation automatically ended except
for continuous burst length. When continuous burst length is set, read/write is endless unless it is terminated by
the rising edge of CE1.
• Single Write
Single write is synchronous write operation with Burst Length = 1. The device can be configured either to "Burst
Read & Single Write" or to "Burst Read & Burst Write" through CR set sequence. Once the device is configured
to "Burst Read & Single Write" mode, the burst length for synchronous write operation is always fixed 1 regardless
of BL values set in CR, while burst length for read is in accordance with BL values set in CR.
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