MC9S08AC16_08 Datasheet, PDF (99/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 6 Parallel Input/Output
6.7.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS)
In addition to the I/O control, port D pins are controlled by the registers listed below.
7
6
5
4
3
2
R
R
R
R
R
PTDPE3
PTDPE2
W
Reset
0
0
0
0
0
0
Figure 6-27. Internal Pullup Enable for Port D (PTDPE)¹
1 _{Bits 7 through 4 are reserved bits that must always be written to 0.}
1
PTDPE1
0
0
PTDPE0
0
Table 6-18. PTDPE Register Field Descriptions
Field
Description
3:0
PTDPE[3:0]
Internal Pullup Enable for Port D Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTD pin. For port D pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port D bit n.
1 Internal pullup device enabled for port D bit n.
7
6
5
4
3
2
1
R
R
R
R
R
PTDSE3
PTDSE2
PTDSE1
W
Reset
0
0
0
0
0
0
0
Figure 6-28. Output Slew Rate Control Enable for Port D (PTDSE)¹
1 _{Bits 7 through 4 are reserved bits that must always be written to 0.}
0
PTDSE0
0
Table 6-19. PTDSE Register Field Descriptions
Field
Description
3:0
PTDSE[3:0]
Output Slew Rate Control Enable for Port D Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.
MC9S08AC16 Series Data Sheet, Rev. 6
Freescale Semiconductor
99