MC9S08AC16_08 Datasheet, PDF (75/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 5 Resets, Interrupts, and System Configuration
5.9.5 System MCLK Control Register (SMCLK)
This register is used to control the MCLK clock output.
7
6
5
4
3
2
1
0
R
0
0
0
0
MPE
W
MCSEL
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-6. System MCLK Control Register (SMCLK)
Table 5-7. SMCLK Register Field Descriptions
Field
4
MPE
2:0
MCSEL
Description
MCLK Pin Enable — This bit is used to enable the MCLK function.
0 MCLK output disabled.
1 MCLK output enabled on PTC2 pin.
MCLK Divide Select — These bits are used to select the divide ratio for the MCLK output according to the
formula below when the MCSEL bits are not equal to all zeroes. In the case that the MCSEL bits are all zero and
MPE is set, the pin is driven low. See Equation 5-1.
MCLK frequency = Bus Clock frequency ÷ (2 * MCSEL)
Eqn. 5-1
MC9S08AC16 Series Data Sheet, Rev. 6
Freescale Semiconductor
75