MC9S08AC16_08 Datasheet, PDF (104/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 6 Parallel Input/Output
6.7.11 Port F I/O Registers (PTFD and PTFDD)
Port F parallel I/O function is controlled by the registers listed below.
7
6
5
4
3
2
R
R
PTFD6
PTFD5
PTFD4
R
R
W
Reset
0
0
0
0
0
0
Figure 6-35. Port F Data Register (PTFD)¹
1 _{Bits 7, 3 and 2 are reserved bits that must always be written to 0.}
1
PTFD1
0
0
PTFD0
0
Table 6-26. PTFD Register Field Descriptions
Field
6:4, 1:0
PTFDn
Description
Port F Data Register Bits— For port F pins that are inputs, reads return the logic level on the pin. For port F
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
7
6
5
4
3
2
R
R
PTFDD6
PTFDD5
PTFDD4
R
R
W
Reset
0
0
0
0
0
0
Figure 6-36. Data Direction for Port F (PTFDD)¹
1 _{Bits 7, 3 and 2 are reserved bits that must always be written to 0.}
1
PTFDD1
0
0
PTFDD0
0
Table 6-27. PTFDD Register Field Descriptions
Field
Description
6:4, 1:0
PTFDDn
Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for
PTFD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.
MC9S08AC16 Series Data Sheet, Rev. 6
104
Freescale Semiconductor