MC9S08AC16_08 Datasheet, PDF (93/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 6 Parallel Input/Output
6.7.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS)
In addition to the I/O control, port B pins are controlled by the registers listed below.
7
6
5
4
3
2
R
R
R
R
R
PTBPE3
PTBPE2
W
Reset
0
0
0
0
0
0
Figure 6-17. Internal Pullup Enable for Port B (PTBPE)¹
1 _{Bits 7 through 4 are reserved bits that must always be written to 0.}
1
PTBPE1
0
0
PTBPE0
0
Table 6-8. PTBPE Register Field Descriptions
Field
Description
3:0
PTBPE[3:0]
Internal Pullup Enable for Port B Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port B bit n.
1 Internal pullup device enabled for port B bit n.
7
6
5
4
3
2
R
R
R
R
R
PTBSE3
PTBSE2
W
Reset
0
0
0
0
0
0
Figure 6-18. Output Slew Rate Control Enable (PTBSE)¹
1 _{Bits 7 through 4 are reserved bits that must always be written to 0.}
1
PTBSE1
0
0
PTBSE0
0
Table 6-9. PTBSE Register Field Descriptions
Field
Description
3:0
PTBSE[3:0]
Output Slew Rate Control Enable for Port B Bits— Each of these control bits determine whether output slew
rate control is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port B bit n.
1 Output slew rate control enabled for port B bit n.
MC9S08AC16 Series Data Sheet, Rev. 6
Freescale Semiconductor
93