MC9S08AC16_08 Datasheet, PDF (64/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 5 Resets, Interrupts, and System Configuration
• Computer operating properly (COP) timer
• Illegal opcode detect
• Illegal address detect
• Background debug forced reset
• The reset pin (RESET)
• Clock generator loss of lock and loss of clock reset
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register.
5.4 Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COPE becomes set in SOPT enabling the COP watchdog (see Section 5.9.4, “System
Options Register (SOPT),” for additional information). If the COP watchdog is not used in an application,
it can be disabled by clearing COPE. The COP counter is reset by writing any value to the address of SRS.
This write does not affect the data in the read-only SRS. Instead, the act of writing to this address is
decoded and sends a reset signal to the COP counter.
The COPCLKS bit in SOPT2 (see Section 5.9.10, “System Options Register 2 (SOPT2),” for additional
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 1-kHz clock source. With each clock source, there is an associated short and long
time-out controlled by COPT in SOPT. Table 5-1 summaries the control functions of the COPCLKS and
COPT bits. The COP watchdog defaults to operation from the bus clock source and the associated long
time-out (2¹⁸ cycles).
Table 5-1. COP Configuration Options
Control Bits
COPCLKS
COPT
Clock Source
COP Overflow Count
0
0
~1 kHz
2⁵ cycles (32 ms)¹
0
1
~1 kHz
2⁸ cycles (256 ms)¹
1
0
Bus
2¹³ cycles
1
1
Bus
2¹⁸ cycles
1 _{Values are shown in this column based on tRTI = 1 ms. See tRTI in the appendix}
Section A.10.1, “Control Timing,” for the tolerance of this value.
Even if the application will use the reset default settings of COPE, COPCLKS, and COPT, the user must
write to the write-once SOPT and SOPT2 registers during reset initialization to lock in the settings. That
way, they cannot be changed accidentally if the application program gets lost. The initial writes to SOPT
and SOPT2 will reset the COP counter.
MC9S08AC16 Series Data Sheet, Rev. 6
64
Freescale Semiconductor