MC9S08AC16_08 Datasheet, PDF (105/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 6 Parallel Input/Output
6.7.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS)
In addition to the I/O control, port F pins are controlled by the registers listed below.
7
6
5
4
3
2
R
R
PTFPE6
PTFPE5
PTFPE4
R
R
W
Reset
0
0
0
0
0
0
Figure 6-37. Internal Pullup Enable for Port F (PTFPE)¹
1 _{Bits 7, 3 and 2 are reserved bits that must always be written to 0.}
1
PTFPE1
0
0
PTFPE0
0
Table 6-28. PTFPE Register Field Descriptions
Field
Description
6:4, 1:0
PTFPEn]
Internal Pullup Enable for Port F Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTF pin. For port F pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port F bit n.
1 Internal pullup device enabled for port F bit n.
7
6
5
4
3
R
R
PTFSE6
PTFSE5
PTFSE4
R
W
2
1
R
PTFSE1
Reset
0
0
0
0
0
0
0
Figure 6-38. Output Slew Rate Control Enable for Port F (PTFSE)¹
1 _{Bits 7, 3 and 2 are reserved bits that must always be written to 0.}
0
PTFSE0
0
Table 6-29. PTFSE Register Field Descriptions
Field
6:4, 1:0
PTFSEn
Description
Output Slew Rate Control Enable for Port F Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTF pin. For port F pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port F bit n.
1 Output slew rate control enabled for port F bit n.
MC9S08AC16 Series Data Sheet, Rev. 6
Freescale Semiconductor
105