MC9S08AC16_08 Datasheet, PDF (91/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 6 Parallel Input/Output
7
6
5
4
3
2
R
PTASE7
R
R
R
R
PTASE2
W
Reset
0
0
0
0
0
0
Figure 6-13. Internal Pullup Enable for Port A (PTASE)¹
1 _{Bits 6 through 3 are reserved bits that must always be written to 0.}
1
PTASE1
0
0
PTASE0
0
Table 6-4. PTASE Register Field Descriptions
Field
Description
7, 2:0
PTASEn]
Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
7
6
5
4
3
2
R
PTADS7
R
R
R
R
PTADS2
W
Reset
0
0
0
0
0
0
Figure 6-14. Internal Pullup Enable for Port A (PTASE)¹
1 _{Bits 6 through 3 are reserved bits that must always be written to 0.}
1
PTADS1
0
0
PTADS0
0
Table 6-5. PTASE Register Field Descriptions
Field
Description
7, 2:0
PTADSn
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin.
0 Low output drive enabled for port A bit n.
1 High output drive enabled for port A bit n.
MC9S08AC16 Series Data Sheet, Rev. 6
Freescale Semiconductor
91