MC9S08AC16_08 Datasheet, PDF (86/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 6 Parallel Input/Output
Refer to Chapter 11, “Serial Communications Interface (S08SCIV4)” for more information about using
port E pins as SCI pins.
Refer to Chapter 12, “Serial Peripheral Interface (S08SPIV3)” for more information about using port E
pins as SPI pins.
Refer to Chapter 10, “Timer/PWM (S08TPMV3)” for more information about using port E pins as TPM
channel pins.
6.3.6 Port F
Port F
Bit 7
6
5
4
3
2
1
Bit 0
MCU Pin: R
PTF6
PTF5/
PTF4/
TPM2CH1 TPM2CH0
R
Figure 6-7. Port F Pin Names
R
PTF1/
PTF0/
TPM1CH3 TPM1CH2
Port F pins are general-purpose I/O pins. Parallel I/O function is controlled by the port F data (PTFD) and
data direction (PTFDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTFPE), slew rate control (PTFSE), and drive strength select (PTFDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port F general-purpose I/O is shared with TPM1 and TPM2 timer channels. When any of these shared
functions is enabled, the direction, input or output, is controlled by the shared function and not by the data
direction register of the parallel I/O port. Also, for pins which are configured as outputs by the shared
function, the output data is controlled by the shared function and not by the port data register.
Refer to Chapter 10, “Timer/PWM (S08TPMV3)” for more information about using port F pins as TPM
channel pins.
6.3.7 Port G
Port G
Bit 7
6
5
4
3
2
1
Bit 0
MCU Pin: 0
PTG6/ PTG5/ PTG4/ PTG3/
EXTAL XTAL KBIP4 KBIP3
Figure 6-8. Port G Pin Names
PTG2/
KBIP2
PTG1/
KBIP1
PTG0/
KBIP0
Port G pins are general-purpose I/O pins. Parallel I/O function is controlled by the port G data (PTGD) and
data direction (PTGDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTGPE), slew rate control (PTGSE), and drive strength select (PTGDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port G general-purpose I/O is shared with KBI, XTAL, and EXTAL. When a pin is enabled as a KBI input,
the pin functions as an input regardless of the state of the associated PTG data direction register bit. When
MC9S08AC16 Series Data Sheet, Rev. 6
86
Freescale Semiconductor