MC9S08AC16_08 Datasheet, PDF (165/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 10
Timer/PWM (S08TPMV3)
10.1 Introduction
The MC9S08AC16 Series includes three independent timer/PWM (TPM) modules which support
traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on
each channel. A control bit in each TPM configures all channels in that timer to operate as center-aligned
PWM functions. In each TPM, timing functions are based on a separate 16-bit counter with prescaler and
modulo features to control frequency and range (period between overflows) of the time reference. This
timing system is ideally suited for a wide range of control applications, and the center-aligned PWM
capability on the TPM extends the field of applications to motor control in small appliances.
The use of the fixed system clock, XCLK, as the clock source for any of the TPM modules allows the TPM
prescaler to run using the oscillator rate divided by two (ICGERCLK/2). This option is only available if
the ICG is configured in FEE mode and the proper conditions are met (see Section 8.4.11, “Fixed
Frequency Clock”). In all other ICG modes this selection is redundant because XCLK is the same as
BUSCLK.
An external clock source can be connected to the TPMCLK pin. The maximum frequency for TPMCLK
is the bus clock frequency divided by 4. All three TPM modules can independently select TPMCLK as the
clock source.
NOTE
The MC9S08AW16A and the MC9S08AW8A devices do not implement
TPM3. These devices only have the 4-channel TPM1 and the 2-channel
TPM2 on 44-and 48-pin packages. These devices only have 2-channel
TPM1 and 2-channel TPM2 on 32-pin packages.
10.2 Features
The timer system in the MC9S08AC16 Series includes a 4-channel TPM1 (2-channel TPM1 on 32-bit
package option), a separate 2-channel TPM2 and a separate 2-channel TPM3. Timer system features
include:
• A total of up to eight channels:
— Each channel may be input capture, output compare, or buffered edge-aligned PWM
— Rising-edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs
• Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all
channels
• Clock source to prescaler for each TPM is independently selectable as bus clock, fixed system
clock, or an external pin:
MC9S08AC16 Series Data Sheet, Rev. 6
Freescale Semiconductor
165