MC9S08AC16_08 Datasheet, PDF (181/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 10 Timer/PWM Module (S08TPMV3)
When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register)
such that the buffer latches remain in the state they were in when the BDM became active, even if one or
both halves of the modulo register are written while BDM is active. Any write to the modulo registers
bypasses the buffer latches and directly writes to the modulo register while BDM is active.
7
6
5
4
3
2
R
Bit 15
14
13
12
11
10
W
1
0
9
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure 10-10. TPM Counter Modulo Register High (TPMxMODH)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 10-11. TPM Counter Modulo Register Low (TPMxMODL)
Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first
counter overflow will occur.
10.5.4 TPM Channel n Status and Control Register (TPMxCnSC)
TPMxCnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt
enable, channel configuration, and pin function.
7
6
5
4
3
2
1
0
R CHnF
0
0
CHnIE
MSnB
MSnA
ELSnB
ELSnA
W
0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-12. TPM Channel n Status and Control Register (TPMxCnSC)
MC9S08AC16 Series Data Sheet, Rev. 6
Freescale Semiconductor
181