MC9S08AC16_08 Datasheet, PDF (83/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 6 Parallel Input/Output
6.2 Features
Parallel I/O and Pin Control features, depending on package choice, include:
• A total of 38 general-purpose I/O pins in seven ports
• Hysteresis input buffers
• Software-controlled pullups on each input pin
• Software-controlled slew rate output buffers
• Four port A pins
• Four port B pins shared with ADC1 and TPM3¹
• Six port C pins shared with SCI2, IIC1, and MCLK
• Four port D pins shared with ADC1, KBI, and TPM1 and TPM2 external clock inputs
• Eight port E pins shared with SCI1, TPM1, and SPI1
• Five port F pins shared with TPM1 and TPM2
• Seven port G pins shared with XTAL, EXTAL, and KBI
6.3 Pin Descriptions
The MC9S08AC16 Series has a total of 38 parallel I/O pins in seven ports (PTA–PTG). Not all pins are
bonded out in all packages. Consult the pin assignment in Chapter 2, “Pins and Connections,” for available
parallel I/O pins. All of these pins are available for general-purpose I/O when they are not used by other
on-chip peripheral systems.
After reset, the shared peripheral functions are disabled so that the pins are controlled by the parallel I/O.
All of the parallel I/O are configured as inputs (PTxDDn = 0). The pin control functions for each pin are
configured as follows: slew rate control enabled (PTxSEn = 1), low drive strength selected (PTxDSn = 0),
and internal pullups disabled (PTxPEn = 0).
The following paragraphs discuss each port and the software controls that determine each pin’s use.
6.3.1 Port A
Port A
Bit 7
6
5
4
3
2
1
Bit 0
MCU Pin: PTA7
R
R
R
R
Figure 6-2. Port A Pin Names
PTA2
PTA1
PTA0
Port A pins are general-purpose I/O pins. Parallel I/O function is controlled by the port A data (PTAD) and
data direction (PTADD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTAPE), slew rate control (PTASE), and drive strength select (PTADS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
1. TPM3 is not available on MC9S08AWxxA devices.
MC9S08AC16 Series Data Sheet, Rev. 6
Freescale Semiconductor
83