MC9S08AC16_08 Datasheet, PDF (318/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Appendix A Electrical Characteristics and Timing Specifications
Table A-11. ICG Frequency Specifications (continued)
(V_DDA = V_DDA (min) to V_DDA (max), Temperature Range = –40 to 125°C Ambient)
Num
C
Characteristic
Symbol
Min
Typ¹
Max
Unit
9
Self-clock mode (ICGOUT) frequency ²
f_Self
f_ICGDCLKmin
f_ICGDCLKmax MHz
10
Self-clock mode reset (ICGOUT) frequency
f_{Self_reset}
5.5
8
10.5
MHz
Loss of reference frequency ³
11
Low range
High range
f_LOR
5
50
25
500
kHz
12
Loss of DCO frequency ⁴
f_LOD
0.5
1.5
MHz
Crystal start-up time ^{5, 6}
13
Low range
High range
t
CSTL
t
CSTH
—
430
—
—
4
—
ms
FLL lock time ^{, 7}
14
Low range
High range
t_Lockl
t_Lockh
—
—
2
ms
2
15
FLL frequency unlock range
n_Unlock
–4*N
4*N
counts
16
FLL frequency lock range
n_Lock
–2*N
17
ICGOUT period jitter, ^{, 8} measured at f_ICGOUT Max
Long term jitter (averaged over 2 ms interval)
C_Jitter
—
2*N
counts
0.2
% f_ICG
MC9S08ACxx: Internal oscillator deviation from
trimmed frequency⁹
V_DD = 2.7 – 5.5 V, (constant temperature)
V_DD = 5.0 V ±10%, –40° C to 125°C
ACC_int
—
—
± 0.5
±0.5
±2
±2
%
18
S9S08AWxxA: Internal oscillator deviation from
trimmed frequency¹⁰
C
V_DD = 2.7 – 5.5 V, (constant temperature)
P
V_DD = 5.0 V ±10%, –40° C to 85°C
ACC_int
—
± 0.5
±1.5
—
±0.5
±1.5
%
P
V_DD = 5.0 V ±10%, –40° C to 125°C
—
±0.5
±2.0
1 _{Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.}
2 _{Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop.}
3 _{Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it}
is not in the desired range.
4 _{Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode}
(if an external reference exists) if it is not in the desired range.
5 _{This parameter is characterized before qualification rather than 100% tested.}
6 _{Proper PC board layout procedures must be followed to achieve specifications.}
7 _{This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external modes.}
If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fICGOUT.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V_DDA and V_SSA and variation in crystal oscillator frequency increase the C_Jitter percentage for
a given interval.
9 _{See Figure A-9.}
10 _{See Figure A-9.}
MC9S08AC16 Series Data Sheet, Rev. 6
318
Freescale Semiconductor