MC9S08AC16_08 Datasheet, PDF (52/344 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 4 Memory
burst programming. The FCDIV register must be initialized before using any FLASH commands. This
only must be done once following a reset.
WRITE TO FCDIV ^{(Note 1)}
Note 1: Required only once after reset.
FLASH PROGRAM AND
ERASE FLOW
START
0
FACCERR ?
1
CLEAR ERROR
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (Note 2)
Note 2: Wait at least four bus cycles
before checking FCBEF or FCCF.
FPVIOL OR
YES
FACCERR ?
NO
ERROR EXIT
0
FCCF ?
1
DONE
Figure 4-2. FLASH Program and Erase Flowchart
4.4.4 Burst Program Execution
The burst program command is used to program sequential bytes of data in less time than would be
required using the standard program command. This is possible because the high voltage to the FLASH
array does not need to be disabled between program operations. Ordinarily, when a program or erase
command is issued, an internal charge pump associated with the FLASH memory must be enabled to
supply high voltage to the array. Upon completion of the command, the charge pump is turned off. When
a burst program command is issued, the charge pump is enabled and then remains enabled after completion
of the burst program operation if these two conditions are met:
• The next burst program command has been queued before the current program operation has
completed.
MC9S08AC16 Series Data Sheet, Rev. 6
52
Freescale Semiconductor