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MC68HC05C9A Datasheet, PDF (98/124 Pages) Freescale Semiconductor, Inc – Microcontrollers
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Electrical Specifications
12.10 3.3-Volt Serial Peripheral Interface Timing
No.
Characteristic(1)
Symbol
Min
Max
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
0.5
dc
1.0
Cycle time
1
Master
Slave
tCYC(M)
2.0
—
tCYC(S)
1.0
—
Enable lead time
2
Master
Slave
tLead(M)
Note 2
—
tLead(S)
500
—
Enable lag time
3
Master
Slave
tLag(M)
tLag(S)
Note 2
—
1.5
—
Clock (SCK) high time
4
Master
Slave
tW(SCKH)M
720
—
tW(SCKH)S
400
—
Clock (SCK) low time
5
Master
Slave
tW(SCKL)M
720
—
tW(SCKL)S
400
—
Data setup time (inputs)
6
Master
Slave
tSU(M)
tSU(S)
200
—
200
—
Data hold time (inputs)
7
Master
Slave
8
Slave access time (time to data active
from high-impedance state)
tH(M)
tH(S)
tA
200
—
200
—
0
250
9 Slave disable time (hold time to high-impedance state)
Data valid
10
Master (before capture edge)
Slave (after enable edge)(3)
tDIS
tV(M)
tV(S)
—
500
0.25
—
—
500
Data hold time (outputs)
11
Master (after capture edge)
Slave (after enable edge)
tHO(M)
tHO(S)
0.25
—
0
—
Rise time (20% VDD to 70% VDD, CL = 200 pF)
12
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tRM
—
200
tRS
—
2.0
Fall time (70% VDD to 20% VDD, CL = 200 pF)
13
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tFM
—
200
tFS
—
2.0
1. VDD = 3.3 Vdc ± 0.3 Vdc; VSS = 0 Vdc, TA = –40 to +125°C, unless otherwise noted. Refer to Figure 12-9 and
Figure 12-10 for timing diagrams.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
Unit
fOP
MHz
tCYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCYC(M)
ns
tCYC(M)
ns
ns
µs
ns
µs
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
98
Freescale Semiconductor
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