MC68HC05C9A Datasheet, PDF (66/124 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
SS
SCK
SCK
SCK
SCK
MISO/MOSI
MSB
6
5
4
3
2
1
0
CPOL = 0
CPHA = 0
CPOL = 0
CPHA = 1
CPOL = 1
CPHA = 0
CPOL = 1
CPHA = 1
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
10.3.2 Master Out/Slave In (MOSI)
The MOSI line is configured as an output in a master device and as an input in a slave device. It is one
of the two lines that transfer serial data in one direction with the most significant bit sent first.
10.3.3 Serial Clock (SCK)
The master clock is used to synchronize data movement both in and out of the device through its MOSI
and MISO lines. The master and slave devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master device, this line becomes an input
on a slave device.
As shown in Figure 10-1, four possible timing relationships may be chosen by using control bits CPOL
and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the MOSI line a half cycle before the clock
edge (SCK), in order for the slave device to latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a slave device,
SPR0 and SPR1 have no effect on the operation of the SPI.
10.3.4 Slave Select (SS)
The slave select (SS) input line is used to select a slave device. It has to be low prior to data transactions
and must stay low for the duration of the transaction.The SS line on the master must be tied high. In
master mode, if the SS pin is pulled low during a transmission, a mode fault error flag (MODF) is set in
the SPSR. In master mode the SS pin can be selected as a general-purpose output by writing a 1 in bit 5
of the port D data direction register, thus disabling the mode fault circuit.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high
between successive characters in an SPI message. When CPHA = 1, SS may be left low for several SPI
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
66
Freescale Semiconductor